The present invention relates to memories, and more particularly to a dynamic random access memory (DRAM) architectures with increased densities.
Because a DRAM memory cell includes just a single access transistor and a storage capacitor, DRAM offers dramatic density advantages over static random access memory (SRAM), which typically requires a six transistor (6-T) memory cell. In contrast to SRAM, a DRAM cell will only change the voltage on its corresponding bit line slightly during read operations. Having been coupled to the bit line, the storage capacitor in a DRAM cell must be then be restored after a read operation. Thus, DRAM sense amplifiers require a regenerative latching ability to drive the bit line “full rail” after a read operation. If the sense amplifier determines that the storage capacitor was charged to VDD, the bit line is then driven to VDD to restore the charge on the storage capacitor. On the other hand, if the sense amplifier determines that the storage capacitor was not charged, the bit line is grounded to discharge the storage capacitor. Moreover, the charge on DRAM storage capacitors continually leaks away, requiring constant refreshing. SRAM cells require no such refreshing. In addition, because the 6-T SRAM cell can drive its value onto a bit line during read operations, SRAM is generally substantially faster than DRAM.
As a result of the density vs. speed advantages of SRAM and DRAM, SRAM is faster but more expensive and thus reserved for more time-critical operations such as a microprocessor's cache. To reduce costs, the remaining RAM for a microprocessor is then typically implemented as DRAM. However, because DRAM operation speed is constantly being improved, the use of embedded DRAM in integrated circuits is becoming more popular in high-performance applications that traditionally demanded embedded SRAM. Nevertheless, the choice between DRAM and SRAM is often guided by the density vs. speed tradeoffs discussed above. Accordingly, designers strive to increase DRAM density.
The challenges to increasing DRAM density may be better appreciated through discussion of a conventional DRAM 100 illustrated in FIG. 1. A word line WL0 controls the gate of an access NMOS transistor M0 whose drain couples to a bit line Bx. The source of access transistor M0 couples to a storage capacitor C0. Thus, access transistor M0 and storage capacitor C0 form a DRAM memory cell that is accessed by raising the voltage on word line WL0. In response to this voltage rise, any charge on capacitor C0 couples to bit line Bx. A sense amplifier reads the contents of the accessed memory cell by detecting a resulting voltage change on bit line Bx.
The sense amplifier detects the voltage change by comparing the voltage on bit line Bx to a neighboring bit line such as a bit line B. Before this comparison is made, bit lines Bx and B are pre-charged to a voltage VDD/2 by pre-charge circuitry. If the comparison indicates that bit line Bx is higher in voltage than bit line B, downstream decoding logic (not illustrated) will assume that the storage capacitor C0 had previously been charged to VDD. If the comparison indicates that bit line B is higher in voltage than bit line Bx, the decoding logic will assume that storage capacitor C0 had previously been discharged. In this fashion, a decision is made as to the binary contents of the memory cell. Having read the contents of the memory cell, the sense amplifier will restore the memory cell using a regenerative latch. An analogous access may be made to a memory cell comprised of access transistor M1 and a storage capacitor C1 by raising a word line WL1, and so on.
Each bit line has an inherent capacitance that is typically an order of magnitude greater than the capacitance of the storage capacitors. This difference in capacitance is exacerbated as the number of memory cells accessible by a sense amplifier is increased. For example, should DRAM 100 be first implemented with an integer number “N” of word lines, the length of the bit lines will have to double if N is increased to 2*N (assuming the same semiconductor process dimensions in both cases). The bit line capacitance will thus double as well, thereby decreasing the voltage change when a memory cell is accessed. As a result, the maximum number of memory cell rows per sense amplifier in a conventional trench-capacitor DRAM is limited to, for example, 512 rows per sense amplifier. The maximum number of memory cell rows per sense amplifier is much lower if storage transistors are used to form the memory cells such as a maximum of 8 to 16 rows.
One of the limiting factors in sensing ever-smaller voltage changes as DRAM density is increased is the non-ideal characteristic of sense amplifiers. A conventional sense amplifier 200 is illustrated in FIG. 2. This sense amplifier includes a differential amplifier 205 that compares a voltage P derived from bit line B (FIG. 1) at its positive input to a voltage N derived from bit line Bx (FIG. 1) at its negative input. If voltage P is higher than the voltage N, the voltage difference is amplified onto differential outputs P0 and N0 by the differential amplifier's gain. A regenerative latch 210 would then drive output P full rail to VDD and ground output N. Conversely, if voltage N is higher than voltage P, the regenerative latch drives output N full rail to VDD and grounds output P.
Should both differential inputs, however, be at the same voltage (such as the pre-charge voltage VDD/2), the regenerative latch operation just described may not take place correctly. Instead, because of offset imperfections in the differential amplifier, P0 (for example) output may be driven higher than N0 despite the equal voltages at the inputs. In turn, this offset limits the sensitivity of the sense amplifier operation. For example, suppose bit line B should be higher in voltage than bit line Bx during a read operation. If the storage capacitance is too small with regard to the bit line capacitance, the offset within the differential amplifier may drive the regenerative latch to pull output N full rail, leading to an erroneous reading.
It may be seen that other issues affect sense amplifier decisions. For example, suppose both bit lines are discharged to VSS (ground potential) prior to sensing. Such a scenario favors the sensing of charged memory cells as opposed to discharged memory cells. Conversely, if both bit lines are charged to VDD, the sensing of discharged memory cells is favored over charged memory cells. The favoring of one bit decision (declaring a binary one or a binary zero as the memory cell contents) over another may be exacerbated as density increases. Accordingly, there is a need in the art for improved DRAM architectures that address such common-mode effects on bit decisions.
As discussed above, the storage capacitance vs. bit line capacitance is a limiting factor for DRAM density. By increasing the storage capacitance, a sense amplifier can better decide what binary contents are being stored. However, the increased storage capacitance generally leads to increased memory cell size, thereby diminishing density. Accordingly, there is a need in the art for improved DRAM memory cell architectures that maximize achievable density.
Another factor affecting density is power consumption. Because DRAMs perform destructive reads, the accessed cell contents must be restored after read operations. In general, all memory cells in a row coupled to a word line will be accessed as that word line is asserted. To limit the number of memory cells that must be restored upon any given word line assertion, it is known to use even and odd word lines such that each row of memory cells associates with two word lines. However, such a memory will still access half the memory cells in a row upon the assertion of a word line. As memory densities increase, such an architecture will still suffer from appreciable power losses during read (and refresh) operations. Accordingly, there is a need in the art for improved DRAM architectures that limit the power consumption during read and refresh operations.